Asymmetric-channel memory system

ABSTRACT

A memory-control integrated circuit includes internal data conductors, steering circuitry and distinct first and second data interfaces, the first data interface having twice as many input/output (I/O) transceivers as the second data interface. In a first memory system configuration in which only the first data interface is coupled to a memory module, the steering circuitry couples all the internal data conductors exclusively to the I/O transceivers of the first data interface. In a second memory system configuration in which the first and second data interfaces are coupled to respective memory modules, the steering circuitry couples a first half of the internal data conductors exclusively to the I/O transceivers of the second data interface while a second half of the internal data conductors remains exclusively coupled to half the I/O transceivers of the first data interface.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.14/874,324 filed Oct. 2, 2015 (now U.S. Pat. No. 9,632,956), which is acontinuation of U.S. patent application Ser. No. 13/499,029 filed Mar.29, 2012 (now U.S. Pat. No. 9,183,166), which is a 35 U.S.C. § 371 U.S.National Stage of International Patent Application No. PCT/US2010/051318filed Oct. 4, 2010, which claims priority to U.S. Provisional PatentApplication No. 61/286,371 filed Dec. 14, 2009. Each of theabove-identified patent applications is hereby incorporated by referencein its entirety.

TECHNICAL FIELD

The present invention relates generally to the field of data processingand more particularly to high-bandwidth memory systems.

BACKGROUND

Modular memories are commonly used in computers and other electronicsystems that may require after-market storage-capacity expansion. Forexample, multiple memory-module sockets may be coupled to a memorycontroller via a shared memory channel, with each socket being coupledto the memory channel via a stub path. Memory modules are initiallyinstalled in fewer than all the sockets so that one or more additionalmodules may be inserted later to increase (expand) the system storagecapacity. Unfortunately, the stub path coupling each socket to theshared memory channel may present a substantial source of undesirednoise (especially signal reflections), and thus limit signaling ratesand therefore peak memory bandwidth.

Although separate, replicated memory channels could be coupledpoint-to-point between the controller and respective memory-modulesockets, that approach multiplies the number of controller interfacepins and external signal lines by the number of memory-module sockets,driving up cost and limiting the number of expansion sockets that can besupported.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention is illustrated by way of example, and not by wayof limitation, in the figures of the accompanying drawings and in whichlike reference numerals refer to similar elements and in which:

FIG. 1 illustrates an embodiment of a modular, expandable memory systemhaving asymmetric memory channels coupled between a memory interfacedevice and four memory sockets;

FIG. 2 illustrates an embodiment of a generalized input/output (I/O)steering circuit that may be used to support switchable interconnectionsbetween an n-bit wide internal data path and a generalized number ofmodule sockets;

FIGS. 3A and 3B illustrate a more detailed embodiment of an I/O steeringcircuit that switchably couples the lanes of an internal data path toasymmetric memory channels of a four-socket memory system in response toa switch-control value;

FIG. 4 illustrates various alternative dispositions (or locations) ofsteering circuitry within a memory system;

FIG. 5 illustrates exemplary data width adjustments performed to conformthe data interface of a memory module to the memory channel width in anasymmetric-channel memory system; and

FIG. 6 illustrates an exemplary sequence of operations that may becarried out within an asymmetric-channel memory system to determine thesocket loading configuration and program corresponding configurationvalues within a memory interface IC and, if present, programmable-widthmemory devices.

DETAILED DESCRIPTION

An expandable memory system and components thereof that enable signalingbandwidth to be configurably re-allocated among dedicated memorychannels are disclosed in various embodiments. In one embodiment, forexample, memory channels having progressively reduced widths arededicated to respective memory sockets, thus enabling point-to-pointsignaling with respect to each memory socket without signal-compromisingtraversal of unloaded sockets or costly replication of a (full-width)memory channel for each socket. When one or more memory modules areinstalled in previously unoccupied sockets (i.e., to expand the systemstorage capacity), a fraction of the signaling bandwidth allocated tothe previously loaded socket(s) is reallocated to the newly loaded(occupied) sockets. Thus, the net signaling bandwidth may remain fixedas new memory modules are added, but the bandwidth share allocated toeach memory module is diluted (reduced) to account for the increasedmemory module count. Further, recognizing that the bandwidth share dropsprogressively as the module population grows, and by establishing apredefined socket loading order, progressively narrower memory channels(i.e., signaling paths for transfer of read and write data, at least,and possibly other signals) may be coupled to later-loaded sockets.

As an example, because the bandwidth share allocated to each socket(assuming an even distribution) is halved for each doubling of thememory module population, an expansion from a single module populationto a two-module population may be effected by splitting the netsignaling bandwidth (B) allocated to the first-loaded memory socket(i.e., the “base socket”) in two, retaining half of the signalingbandwidth (B/2) for the base socket and re-directing the other half ofthe signaling bandwidth to the first expansion socket. Because the netsignaling bandwidth corresponds to a fixed number of signaling links, L,(i.e., L=B/R, where R is the peak signaling rate of each link), itfollows that the first expansion socket need only be coupled to half asmany signaling links as the base socket. Thus, memory channels havingdifferent numbers of constituent signaling links (i.e., asymmetricmemory channels) are coupled to the two memory sockets—L signaling linksto the base socket and L/2 signaling links to the first expansionsocket. By this arrangement, when a memory module is installed in thebase socket only (i.e., single module configuration), the L links thatconstitute the full-width memory channel to the base socket are all usedto convey information-bearing signals and are thus referred to herein as“live” links, while the L/2 links that constitute the half-width memorychannel to the first expansion socket remain unused and are said to be“dormant.”

By contrast, when a memory module is installed in the first expansionsocket (expanding the memory system capacity), half of the availablesignaling bandwidth is reallocated from the base socket to the firstexpansion socket to establish effective half-width channels to eachsocket. More specifically, the L/2 links that form the half-width memorychannel to the expansion socket (i.e., the “half-width expansionchannel”) are made live, and half of the L links that constitute thefull-width memory channel to the base socket (the “base channel”) arerendered dormant, thereby maintaining a fixed number of live links, L(and therefore a fixed signaling bandwidth), but with increased storagecapacity. As a matter of terminology, the half-width expansion channelis said to be activated (i.e., constituent links transitioned fromdormant to live status), and half of the base channel deactivated, withthe remaining L/2 live links of the base channel forming a half-width“logical channel.”

FIG. 1 illustrates an embodiment of a modular, expandable memory system200 having asymmetric memory channels 211 ₀-211 ₃ coupled between amemory interface IC (integrated circuit) 201 and four memory sockets215. In the example shown and embodiments that follow, each of thememory sockets is assumed to be a memory-module socket (or “modulesocket”) that enables removable insertion of a memory module such as asingle or dual in-line memory module (SIMM or DIMM); a small form-factorcircuit board substrate having multiple integrated circuit memorydevices mounted to one face or both faces and contacts that mate tocounterpart contacts within the module socket. In more generalembodiments, however, a “memory socket” or “socket” may be any structurethat permits post-production installation (and/or removal forreplacement or repair purposes) of memory modules or any othersocket-able memory element including, without limitation, a memorymodule having virtually any practicable form factor, an integratedcircuit memory package that encapsulates or otherwise includes one ormore integrated circuit memory dice, or even a bare integrated circuitdie. Also, the expression “memory interface IC” refers to any integratedcircuit component or device having an interface that enablescommunication of memory control commands (or requests) and correspondingtransfer of read and write data with respect to one or more memorymodules and/or memory devices. Examples of a memory interface ICinclude, without limitation, a memory controller IC (which may be an ICdie dedicated to a memory control function, or an IC such as amicroprocessor or application-specific integrated circuit (ASIC) havingmemory controller circuitry integrated onto the IC die), a memory bufferIC (sometimes referred to as a “buffer-on-board” or “BOB”) to be coupledbetween a memory controller IC and one or more memory modules, or asystem on chip (SoC) that incorporates multiple functional blocks alongwith a memory control function, and so forth.

In the embodiment of FIG. 1, the memory interface IC 201 includes corelogic 203 to carry out the core function(s) of the memory interface IC(e.g., at least a memory control function in a memory controller IC, andat least memory-side-to-controller-side signaling exchange in a memorybuffer IC), and input/output (I/O) steering circuitry 205 that forms asignaling interface for the four module sockets. The core logic 203 andI/O steering circuitry 205 are coupled to one another via internalsignaling path 208 formed by a number (n) of internal signaling links.For simplicity of explanation, the internal signaling path 208 isassumed to be a data path for bi-directional conveyance of read andwrite data between the core logic and the I/O steering circuitry, andone or more internal control paths (not shown) are used to convey memorycontrol information (commands/requests, addresses, timing signals,masking signals, module/rank select signals, configuration information,etc.) for managing operations within any socketed (i.e., installed)memory modules. Similarly, the asymmetric memory channels themselves(collectively, 211) are assumed to be data channels for bidirectionalconveyance of read and write data between the memory interface IC andthe module sockets, and one or more control channels (not shown) areused to convey memory control information to the socketed memorymodules. These assumptions are carried forward in other embodimentsdiscussed below, though in all cases the control information may betransmitted via the data path (e.g., via time-multiplexed operation) andthe separate internal control path and external control channel omitted.Also, while each of the asymmetric memory channels is shown as apoint-to-point signaling link extending between the memory interface IC201 and a single memory-module socket, each of the asymmetric memorychannels in the embodiment of FIG. 1 and any of the embodimentsdiscussed below could alternatively be coupled in multi-drop fashion tomultiple memory-module sockets, or to multiple memory sockets, each ofany type.

Still referring to FIG. 1, the constituent signaling links of theinternal data path 208 are referred to herein as “data lanes” todistinguish them from external “DQ” signaling links that constitute eachmemory channel. Also, for clarity of explanation, the data lanesignaling rate (i.e., the on-chip signaling rate) is assumed to matchthe DQ signaling rate (i.e., the on-chip and off-chip data signalingrates match), so that the bandwidth of the n-lane internal data path 208is matched by a live set of n DQ links within one or more of theasymmetric memory channels 211. In alternative embodiments, signalingrates on the internal data path 208 and asymmetric memory channels 211may be different, with the higher signaling-rate path beingproportionally narrower to equalize the net internal and externalsignaling bandwidths.

As shown, the asymmetric memory channels have respective widthsconfigured according to the expected loading order of the module socketsto which they are connected. More specifically, a full-width memorychannel 211 ₀ (i.e., n DQ links) is coupled to base socket, S0, toallocate the full system bandwidth to a memory module installed in thatsocket in a single-module configuration (i.e., all other socketsempty—also referred to herein as the base configuration, or x1configuration). By contrast, a half-width memory channel (n/2 DQ links)211 ₁ is coupled to the first expansion socket, S1, to enable half thesystem bandwidth to be reallocated from the base socket to the firstexpansion socket when the latter is loaded with a memory module. Thatis, when the system capacity is expanded from the base configuration toa two-module configuration (x2 configuration) through moduleinstallation in S1, half of the memory bandwidth is reallocated from theoriginally inserted memory module to the newly inserted memory module.Accordingly, in the two-module configuration, only half the DQ links ofbase memory channel 211 ₀ are live, and the other half dormant.Following that same approach, quarter-width memory channels (n/4 DQlinks each) 211 ₂, 211 ₃ are coupled to the second and third expansionslots, S2 and S3, to enable respective one-fourth shares of the systembandwidth to be reallocated from sockets S0 and S1 to sockets S2 and S3when those sockets are populated.

The bandwidth reallocation operation may be better appreciated byconsidering that each of the memory channels 211 ₀-211 ₃ and theinternal signaling path 208 to be formed by one or more sets ofsignaling links, referred to herein as signal-link groups, with eachsignal-link group corresponding to the minimum bandwidth share to beallocated to any one of the memory channels 211—that is, a (1/M)th shareof the signaling bandwidth, where M is the number of module sockets, andthus n/M signaling links. Accordingly, in the four-socket example ofFIG. 1, each signal-link group comprises n/4 signaling links so that theinternal data path includes four signal-link groups (each including n/4constituent data lanes) as shown at 215. Similarly, as shown at 217, thebase memory channel 211 ₀ includes four signal-link groups, the firstexpansion channel 211 ₁ (i.e., to socket S1) includes two signal-linkgroups and the second and third expansion channels 211 ₂, 211 ₃ (i.e.,to sockets S2 and S3) each include a single signal-link group. The I/Osteering logic 205, switchably couples the signal-link groups of theinternal data path to respective signal-link groups within one or moreof the memory channels in accordance with the socket loadingconfiguration, thus steering data signals between the internal datalanes 208 and respective external signaling links, and vice-versa. Morespecifically, as shown at 224, in the single-module configuration 225(i.e., base socket loaded only), the four signal-link groups of theinternal path 208 are coupled respectively to the four signal-linkgroups of the base memory channel 211 ₀, thus allocating the full memorysystem bandwidth to the lone memory module in the system. When expandedto the two-module population shown at 227, two of the four signal-linkgroups (i.e., half) of the internal path are reallocated from the basesocket S0 to the first expansion socket S1 to establish a half-widthmemory channel to each installed memory module.

When expanded further to the three-module population shown at 229, thesignal-link groups are allocated unevenly between the three populatedsockets (S0, S1, S2), with the base module in socket S0 maintaining 50%share of the system bandwidth, and the remaining 50% share being splitevenly among the modules in the first and second expansion sockets (S1and S2). In alternative embodiments, particularly where the total systembandwidth permits an even three-way split (e.g., internal data pathwidth evenly divisible by 3), an even distribution of the signalingbandwidth among the three installed memory modules may be supported.

Finally, when expanded to the four-module population shown at 231, thesignaling bandwidth is again distributed evenly, with each of the foursignal-link groups of the internal path being coupled to a signal-linkgroup within a respective one of the four memory channels 2110-2113,thereby allocating a one-fourth bandwidth share to each of the fourinstalled memory modules.

Reflecting on the bandwidth allocation options shown at 224, the numbersof live and dormant signaling links remains constant, regardless of thesocket loading configuration. Thus, when a single memory module isinstalled, the four signal-link groups that constitute base memorychannel 211 ₀ are live, while remaining four signal-link groups thatconstitute memory channels 211 ₁-211 ₃ (i.e., two signal-link groups toS1 and one each to S2 and S3) are dormant. When two memory modules areinstalled, two of the signal-link groups in the base memory channel 211₀ are deactivated and the same number activated in the S1 memory channel211 ₁, thereby maintaining a fixed memory bandwidth. Similarly, whenexpanding from two installed modules to three, one of the signal-linkgroups in the first expansion channel 211 ₁ (i.e., to S1) is deactivatedand the sole constituent signal-link group of the second expansionchannel 211 ₂ is activated. Finally, in the four module configuration,three of the four signal-link groups of base memory channel 211 ₀ aredeactivated, freeing the corresponding three signal-link groups of theinternal data path 208 to be distributed one apiece among the otherthree memory channels 211 ₁-211 ₃ and thus maintaining the same totalmemory bandwidth as other socket loading configurations, butdistributing that bandwidth among the four memory channels to establisha quarter-bandwidth connection to each of the memory modules (225, 227,229 and 231).

FIG. 2 illustrates an embodiment of a generalized I/O steering circuit241 that may implemented on an IC die (e.g., of a memory interface IC orbuffer IC) and used to support switchable interconnections between ann-bit wide internal data path 208 and a generalized number (m) of modulesockets. Again, the individual signaling links of the internal data pathand each memory channel are conceptually divided into signal-link groupsof n/m links each. The m signal-link groups of the internal data path208, one for each of the m module slots, are referred to herein as “lanegroups” to distinguish them from the counterpart DQ signal-link groupsor “DQ groups” (DQ_(G)) that constitute the external memory channels.The I/O steering circuit itself includes a physical signaling interface242 referred to herein alternatively as the input/output (I/O) circuitor PHY (physical-layer signal drivers and receivers), as well as asteering switch 243 that switchably couples lane groups LG₁-LG_(m-1) tothe DQ groups. In the embodiment shown, the physical-layer signaldrivers and receivers are paired (i.e., each pair including an outputdriver and receiver) to form transceivers 250 that are coupledrespectively to interface nodes 251. In one embodiment, the interfacenodes 251 are implemented by contacts disposed on the IC die 240 (i.e.,together with the internal data path 208 and the remainder of the I/Osteering circuitry 241) to enable electrical connection of IC die 240 tothe external signaling links that form the asymmetric memory channels.More generally, the interface nodes 251 may be implemented by anystructure that enables the signal drivers and/or receivers within IC die240 to be coupled directly or indirectly to the external signaling linksthat form the asymmetric memory channels including, for example andwithout limitation, bond pads, contacts, pins, inductive or capacitiveinterconnects and so forth. In the single-ended, bidirectional signalingarrangement shown, each interface node 251 is coupled between arespective signal transceiver 254 and external signal link 255. In adifferential signaling embodiment, two interface nodes are provided perexternal signal link to enable transmission and reception of adifferential data signal (i.e., two complementary signal components perinformation-bearing signal) on the pair of signal lines that constitutethe differential external signaling link.

Continuing with the single-ended embodiment shown, because the basesocket (S0) will receive, at minimum, (1/M)th of the signal bandwidth inany configuration and thus will always be coupled to at least one liveDQ group, one lane group may be dedicated (i.e., coupled via anon-switched and therefore permanent connection) to a corresponding DQgroup for the base socket as shown by permanent coupling 245 betweenlane group LG₀ and the set of interface nodes 251 coupled to a basechannel DQ group. The constituent data lanes of the permanentlyconnected lane group are thus referred to herein as non-switched lanes.By contrast, each of the other lane groups, LG₁-LG_(m-1), may need to bereallocated from the base channel to one of the expansion memorychannels (i.e., to sockets S1-Sm−1) and is thus switchably coupled viasteering switch 243 to the set of interface nodes for either abase-channel DQ group or an expansion-channel DQ group. Accordingly, theconstituent data lanes of these steered or switched lane groups arereferred to as “switched lanes.”

In one embodiment, steering switch 243 includes switching elements 247₁-247 _(m-1) to switchably couple the data lanes of each switched lanegroup to one of N sets of interface nodes for corresponding DQ lanes,where N varies according to the number of different memory channels towhich a given lane group may be allocated. Because each differentallocation option results in the signals of the switched lane groupbeing steered to/from a different DQ group (i.e., steered to/from adifferent memory channel and thus to/from a different socket), theallocation options are referred to herein as “steering options.”Further, in an embodiment in which the number of links allocated tohigher-numbered expansion sockets is halved for each doubling of thesocket count (i.e., base socket S0 coupled to L signaling links, firstexpansion socket S1 coupled to L/2 signaling links, expansion socketsS2-S3 coupled to L/4 signaling links, expansion sockets S4-S7 coupled toL/8 signaling links, etc.), the final lane group is subject to at leastlog₂m steering options (where ‘m’ is the number of module sockets). Forexample, if there are eight module sockets total (base socket, S0, plusseven expansion sockets, S1-S7), then one of the corresponding eightlane groups, LG₀) is permanently coupled to one of the sets of theinterface nodes for the S0 memory channel (i.e., the memory channeldedicated to socket S0), the next lane group, LG₁, may be switchablycoupled to either a set of interface nodes for the S0 memory channel orto a set of interface nodes for the S1 memory channel, the next lanegroup (not specifically shown) may be switchably coupled to a set ofinterface nodes for the S0 memory channel, the S1 memory channel or theS2 memory channel, and so forth with the final lane group beingswitchably coupled to a set of interface nodes for the S0, S1, S3 or S7memory channels. Although numerous different connection arrangements arepossible (including those which permit a more efficient steering switchimplementation as discussed below), the following table presents onepossible combination of bandwidth allocations for each of the loadingconfigurations in an eight socket system:

TABLE 1 Lane Number of Installed Modules Group 1 2 3 4 5 6 7 8 LG₀ S0 S0S0 S0 S0 S0 S0 S0 LG₁ S0 S1 S0 S1 S1 S1 S1 S1 LG₂ S0 S0 S2 S2 S2 S2 S2S2 LG₃ S0 S1 S3 S3 S3 S3 S3 S3 LG₄ S0 S0 S0 S0 S0 S0 S0 S4 LG₅ S0 S1 S0S1 S5 S5 S5 S5 LG₆ S0 S0 S2 S2 S2 S6 S6 S6 LG₇ S0 S1 S3 S3 S3 S3 S7 S7

Reflecting on the bandwidth allocation options of Table 1, each of theswitched lane groups is switched between as few as two and at least asmany as log₂m+1 different steering options. Lane group LG1, for example,is switchably coupled to either socket S0 or socket S1 (two steeringoptions) and thus may be steered by a 1:2 switch element 247 ₁ as shown.By contrast, lane group LG7 is switchably coupled to one of fourdifferent sockets (i.e., log₂8+1=four steering options) so that, in the8-socket example of Table 1, switch element 247 _(m-1) may beimplemented by a 1:4 switch), including socket S0 in the single-module(x1) configuration, socket S1 in the x2 configuration, socket S3 in thex3-x6 configurations and socket S7 in the x7 and x8 configurations.Thus, steering switch may be formed by m−1 switching elements (one foreach of the switched lane groups), including switches having as few astwo steering options (switch selections) per data lane, and switcheshaving at least as many as log₂m+1 steering options. Also, because thenumber of required interface nodes increases by half the base number (n)for each doubling of the number of module sockets, the total number ofinterface nodes is given by n+0.5*n*log₂m (or n+½*n*(S0−1), wheredenotes multiplication. That is, the number of interface nodes isproportional to the log of the socket count (not the socket count itselfas in the replicated-channel system discussed above). Further, thenumber of interface nodes required per memory socket (and thus thememory channel width and maximum allocable fraction of the systembandwidth for that socket) halves with each doubling of the number ofmemory sockets, with the sockets in the last-to-be-loaded half of thesystem having half the minimum number of interface nodes provided to thesockets in the first-to-be-loaded half of the system. Analytically, thenumber of interface nodes per socket in such an embodiment may beexpressed as: n/(2*roundup(log₂X)), where denotes multiplication, ‘X’ isthe socket number (an integer between 1 and m that corresponds to theorder in which the socket is loaded, with socket number 1 being loadedfirst), and “roundup( )” is a function that rounds its argument up tothe nearest integer. For example, in an eight-socket system inaccordance with the foregoing, the number of interface nodes per socketmay be as follows (more or fewer sockets may be provided in alternativeembodiments):

TABLE 2 Socket Socket Interface Nodes Position No. (memory channelwidth) S0 1 n S1 2 n/2 S2 3 n/4 S3 4 n/4 S4 5 n/8 S5 6 n/8 S6 7 n/8 S7 8n/8

FIG. 3A illustrates a more detailed embodiment of an I/O steeringcircuit 280 that switchably couples an n-lane internal data path toasymmetric memory channels of a four-socket memory system in response toa switch-control value (SC). As shown, the number of external signalinglinks per memory channel 211 follow the progressively halved allocationdescribed above in reference to Table 2 (i.e., full-width channel 211 ₀to socket S0, half-width channel 211 ₁ to socket S1, and quarter-widthchannels 211 ₂ and 211 ₃ to sockets S2 and S3, respectively). Referringto detail view 281, the internal data path may be viewed as includingmultiple 4-bit lane fragments, LF₀, LF_((n/4)-1), each supplied to arespective one of 4-bit switching cells 283 ₀-283 _((n/4)-1) forswitched coupling to a counterpart set of external signaling links thatconstitutes (i) a respective fragment of the overall set of externalsignaling links (i.e., one of DQ fragments, DQF₀-DQF_((n/4)-1)) and (ii)a respective fragment of each of the asymmetric memory channels. Thatis, when the switch-control value indicates a single-moduleconfiguration, each of the 4-bit switching cells 283 couples arespective one of the 4-bit lane fragments to the corresponding 4-bitfragment of the base memory channel (i.e., the four links to socket S0),thereby coupling all n lanes of the internal data path 208 tocounterpart signaling links within the full-width (n-bit wide) basememory channel. When an additional module is installed in socket S1, theswitch-control value is changed accordingly to enable each of theswitching cells 283 to reallocate two data lanes within a respective oneof the four-bit lane fragments from the S0 memory channel to thecorresponding two-bit fragment of the S1 memory channel, therebysplitting the internal data path bandwidth between the half-width S1memory channel and half the links of the full-width base memory channel(deactivating the other half of the links within the base memorychannel). When additional modules are installed in sockets S2 and S3(thus fully loading the memory system), the configuration value ischanged to a corresponding state to enable each of the switching cells283 to reallocate three data lanes per lane fragment from the S0 memorychannel to the 1-bit fragments of the S2 and S3 memory channels and toone half (i.e., one link) of the 2-bit fragment of the S1 memorychannel, thus establishing an even 4-way split of the internal data pathbandwidth between the four memory channels.

In the three-module configuration, the internal bandwidth is unevenlyallocated between the base memory channel and the first and secondexpansion channels. In the particular implementation shown, for example,the first expansion channel is allocated half the signaling bandwidth(and thus is coupled to two data lanes per lane fragment), while thebase channel and the second expansion channel are each allocated arespective quarter of the signaling bandwidth (and thus are each coupledto a single data lane per lane fragment). Note that this configurationinvolves allocating more bandwidth to an expansion socket than the basesocket, but provides the advantage of reduced switching circuitry asshown in cell detail view 287. As can be seen, data lane 0 of eachfour-lane fragment is dedicated (coupled without switching and thuspermanently) to link 0 within the counterpart 4-link fragment of thebase memory channel (S0_DQ0), while the remaining three data lanes arecoupled via respective switching elements 291, 293, 295 to one of atleast two signaling links. More specifically, data lane 1 is switchablycoupled to either S0_DQ1 (link DQ1 within the memory channel to socketS0) or S1_DQ0 (link DQ0 within the expansion channel to socket S1) viaswitching element 291, data lane 2 is switchably coupled to eitherS0_DQ2 or S2_DQ0 (the latter being a link within the memory channel tosocket S2) via switching element 293, and data lane 3 is switchablycoupled to either S0_DQ3 (the fourth of the four links of the S0 channelfragment), S1_DQ1 (the second of the two links of the S1 channelfragment) or S3_DQ0 (a link within the memory channel to socket S3) viaswitching element 295. Though depicted as multiplexer/demultiplexercircuits in FIG. 3A, the switching elements 291, 293, 295 may beimplemented by analog switches (e.g., pass gates) or any otherpracticable switching circuits in alternative embodiments. Also, thoughshown as a passive, hardwired connection, the permanent coupling betweenlane 0 and S0_DQ0 may be established through one or more delay matchingelements, including permanently-configured switching elements. Theoverall switching arrangement described above for each of the foursettings of a two-bit switch control value, SC[1:0], is shown in FIG.3B. While a particular socket loading order is presented in FIGS. 3A and3B (i.e., S0→S0/S1→S0/S1/S2→S0/S1/S2/S3), different socket loadingorders may be dictated (e.g., S0→S0/S1→S0/S2/S3→S0/S1/S2/S3) throughchanges in the implementation of switching cells 283. The socketallocated a larger share of the bandwidth than others in unevenallocation arrangements (e.g., the three-module allocation arrangementshown in FIG. 3B in which a larger bandwidth share is allocated tosocket S1 than to sockets S0 or S2) may similarly be changed throughchanges in the implementation of switching cells 283.

FIG. 4 illustrates various alternative dispositions of theabove-described steering circuitry within a memory system. Morespecifically, the steering circuitry may be disposed upstream ordownstream from the physical I/O circuitry to establish the differentmemory control IC implementations shown at 301 and 303, respectively.The steering circuitry may also be omitted from the memory control ICentirely as shown at 305 and instead be disposed externally to thememory control IC, for example within a buffer IC or entirely off-chip,as shown at 307. In the off-chip instance, the steering circuitry may beformed, for example and without limitation, by switching elements formeddirectly on a printed circuit board, such as a motherboard, backplane,line card or the like.

The fundamental function of the steering circuitry remains unchangedwhether disposed upstream of the I/O circuitry as in memory control IC301 (i.e., steering circuit 321 disposed between I/O circuitry 323 andcontroller core logic 311) or downstream of the I/O circuitry as inmemory control IC 303 (i.e., I/O circuit 341 disposed between controllercore logic 311 and steering circuit 343), though implementation detailsmay change. In the former arrangement (steering circuitry disposedbetween controller core and I/O circuitry), separate unidirectionalsteering circuits 325 and 327 may be provided for incoming and outgoingdata flow directions as shown. In that case, the n “logic-side” outputdata lanes (DL_(LO)) are switchably coupled via outbound steeringcircuit 327 to a live subset of a larger number of “PHY-side” outputdata lanes (DL_(PO)) which are then driven, via respective interfacenodes, onto a corresponding subset of live external signaling links (DQ)by output drivers 331. Inbound steering circuit 325 performs the reversefunction, steering signals received via the live subset of DQ links,receiver circuits 329 and PHY-side input data links (DL_(PI)) to thefull-set of logic-side input data links (DL_(LI)). In thefour-channel/four-socket example shown, the number of PHY-side datalanes (DL_(PI), DL_(PO)) is twice the number of logic-side data lanes(DL_(LI), DL_(LO)), so half the PHY-side input data lanes and half thePHY-side output data lanes are dormant in any loading configuration. Thesignal drivers and/or receivers coupled to dormant data lanes may remainunpowered to reduce power consumption and thermal loading.

Detail view 330 illustrates an example of a digital demultiplexerelement 371 that may be replicated as necessary within steering circuits325 and 327 to provide a unidirectional 1:2 signal steering function. Asshown, an incoming data lane (“Input”) is coupled to the inputs of twologic AND gates 373, 375, with gate 373 having an inverting enable-inputcoupled to switch-control line (SC) and gate 375 having a non-invertingenable-input coupled to the switch-control line. By this arrangement, alogic-low switch-control signal enables AND gate 373 to pass theincoming data signal to output A (“OutA”) and disables AND gate 375 frompassing the data signal to output B (“OutB”). Conversely, a logic-highswitch control signal enables AND gate 375 to pass the incoming datasignal to output B and disables AND gate 373 from passing the datasignal to output A. Demultiplexer element 371 may be used as a buildingblock (or the logic therein extended) to provide a generalized 1:N orN:1 steering function within steering circuits 325 and 327.

When disposed downstream of the I/O circuitry as in memory control IC303, the steering circuitry 343 steers signals between a set of ninternal signaling links, DQ_(I), and a live subset of the larger numberexternal signaling links, DQ_(X). While this approach obviates separatesteering circuits for different data flow directions as in IC 301, adegree of signal attenuation may result from placement of the steeringcircuitry on the output side of the signal drivers (and in front of theinputs to the signal receivers). Also, because link-to-link timingcompensation may be provided within the signal output drivers, anylink-to-link delay skew resulting from, for example timing differencesin switched and non-switched signal paths) may reduce system timingmargin (though this may alternatively be compensated by receiver-sidetiming calibration).

Detail view 350 illustrates an example of a switching element that maybe replicated as necessary within steering circuit 343 (or withinsteering circuits 325 and/or 327) to provide a bidirectional 1:2 (and2:1) or unidirectional signal steering function. As shown, an internalsignal link, DQ_(I) is switchably coupled to each of two externalsignaling links DQ_(XA) and DQ_(XB) via respective pass gates 383 and385. Each of the pass gates is implemented by a pair of parallel-coupledtransistors that is switched on in response to opposite polarity gatevoltages (e.g., PMOS and NMOS transistors in the example shown). Aswitch control signal is provided to the gate terminals of eachpass-gate 383 and 385 in a reverse polarity orientation such that one ofthe pass gates is switched to a conducting state (i.e., switched on) andthe other to a substantially non-conducting state (i.e., switched off),depending on the state of the switch control signal. More specifically,in the embodiment shown, a logic high switch control signal switches onpass gate 383 (through application of the logic high voltage to the NMOStransistor and a logic low voltage, generated by inverted 387, to thePMOS transistor) and switches off pass gate 385 to switchably couple theinternal data link, DQ_(I)[i] exclusively and bidirectionally toexternal link DQ_(XA)[i]. Conversely, a logic low switch-control signalswitches on pass gate 385 (logic low signal applied to PMOS transistorand logic high signal, generated by inverter 387, applied to NMOStransistor) and switches off pass gate 383 to switchably coupleDQ_(I)[i] exclusively and bidirectionally to external link DQ_(XB)[i].Analog switching element may be used as a building block (or the numberof pass gates therein increased) to provide a generalized 1:N or N:1steering function.

As mentioned, the steering circuitry may also be disposed in a buffer IC307, thus enabling use of memory control IC that lacks an internalsteering function (e.g., the buffer IC may provide for capacityexpansion while maintaining a compatible system integration with legacysystems that utilize memory controllers lacking an internal steeringfunction). In the embodiment shown, for example, buffer IC 307 iscoupled between a set of asymmetric memory channels (shown as fourchannels having widths n, n/2, n/4 and n/4) and a memory control IC 305having controller core logic 313 and physical I/O circuitry (drivers 365and receivers 367), but lacking the above-described signal steeringfunction. More specifically, the buffer IC 307 includes a steeringcircuit 361 and memory-side interface (indicated conceptually by linksDQ_(M)) to the asymmetric memory channels, as well as a controller-sideinterface (indicated by links DQ_(C)) to the memory control IC 305. Thebuffer IC may be mounted to a motherboard or other substrate (thusforming a buffer-on-board) or together with the memory control IC and/orother IC's in an integrated circuit package (e.g., a system-in-package).With regard to internal organization, the steering circuit 361 may bedisposed on either side of the physical memory-side signaling interface(e.g., as in memory IC 301 or memory IC 303) and thus implemented usingeither of the multiplexing or switching elements 371 and 381.

The steering circuit may also be implemented entirely off-chip, forexample, by a collection of zero-ohm resistors, mechanical switches orother conductive interconnects that do not significantly compromisesignal integrity (i.e., negligible signal radiation, impedancediscontinuity, etc.) and that may be configured at production time orpost-production time to permit memory capacity selection and/orexpansion.

Still referring to FIG. 4, the detail view labeled “Off-Chip”illustrates an example of an off-chip switching element 391 formed by apair of conductive interconnects 393 and 395 and that may be replicatedas necessary within an off-chip implementation of steering circuit 361to provide a bidirectional or unidirectional signal steering function.As shown, when interconnect 393 is shorted (i.e., controller-side andmemory-side terminals electrically coupled to one another) andinterconnect 395 opened, a controller-side signaling link, DQ_(C) isswitchably coupled to memory side signaling link DQ_(MA), and switchablydecoupled (isolated) from memory side signaling link DQ_(MB).Conversely, when interconnect 395 is shorted (i.e., controller-side andmemory-side terminals electrically coupled to one another) andinterconnect 393 opened, a controller-side signaling link, DQ_(C) isswitchably coupled to memory side signaling link DQ_(MA), and switchablydecoupled (isolated) from memory side signaling link DQ_(MB). Off-chipswitching element 391 may be used as a building block (or the number ofconductive interconnects therein increased) to provide a generalized 1:Nor N:1 steering function.

As discussed in reference to FIG. 1, as bandwidth is reallocated tonewly loaded module sockets, the bandwidth allocated to the previouslyloaded sockets is reduced (i.e., diluted). More specifically, as shownby the different steering configurations at 224, the effective width ofthe memory channel (i.e., the number of live links therein) to one ormore of the previously loaded sockets is reduced, which in turn dictatesa reduction in the number of live links coupled to each of theintegrated circuit memory devices (e.g., dynamic random access memory(DRAM) ICs, static RAM ICs, flash memory ICs, etc) disposed on thecorresponding memory module. That is, the effective width (or logicalwidth) of the data path coupled to each of the memory ICs disposed on apreviously loaded memory module is reduced as bandwidth is reallocatedfrom that module to another memory module. Accordingly, in oneembodiment, whenever a change in the socket loading configurationresults in a decrease or increase in the effective width of the channelcoupled to a given memory module (i.e., effective width of channel to agiven socket is narrowed or widened), the data signaling interfaces ofthe individual memory ICs disposed on that memory module arecorrespondingly narrowed or widened. FIG. 5 illustrates an example ofthis operation in the context of an eight-socket memory system 400having a memory interface IC 401 with an on-chip I/O steering circuit403 that operates generally as described above (and which may be, forexample, a memory control IC or a buffer IC). The eight memory channels405 exhibit progressively halved widths as described in reference totable 2 above so that the minimum physical width of any of the channelsand the minimum logical width (effective width) of any of the memorychannels is n/8. In the particular example shown, the width of theinternal data path 402 is assumed to be 64 bits, yielding memorychannels 405 having widths of 64 bits (S0), 32 bits (S1), 16 bits (S2,S3) and 8 bits (S4, S5, S6, S7), as shown.

Referring to detail view 410 of FIG. 5, a memory module 411 that may beinstalled within each of the memory sockets 407 is assumed for purposesof example to include eight memory ICs 415 ₀-415 ₇ having respective8-bit wide data interfaces coupled to corresponding 8-bit slices of a64-bit module data interface 412. The eight memory ICs (collectively,415) are operated as a memory rank (i.e., selected as a unit forread/write purposes) and each includes, in addition to the 8-bit widedata interface 419, a command interface (not shown), memory core 423 andcontrol logic 421 to access the memory core in response to commandsreceived via the command interface. More specifically, the control logiccoordinates data retrieval and storage operations in response to memoryread and write commands, outputting read data and receiving write datavia the data interface. The control logic 421 may also include aconfiguration register, “creg” (or other configuration control circuit)that may be programmed in response to incoming commands to establishoperating characteristics and modes of the memory device, includingadjusting the effective (logical) width of the data interface 419 to anumber of different settings by disabling one or more of the constituentsignal driver/receiver circuits 425 within the data interface andcorresponding internal circuitry. Thus, in a base system configurationin which a memory module is installed in socket S0 only (all othersockets empty), each memory device 415 of the installed memory modulemay be programmed to employ the full physical width of its respectivedata interface 419 (i.e., logical width=physical width=8 bits), thusestablishing a 64-bit module data width to match the 64-bit widefull-width memory channel allocated to socket S0 as shown at 430. When,the memory system is expanded to a two-module configuration (memorymodules in slots S0 and S1), the S0 memory module may be reprogrammed(i.e., by issuing a programming command and corresponding controlregister value) to change the data interface 419 width from x8 to x4(i.e., disabling half the data I/O circuits as shown in dashed outlinein view 432) to establish a 32-bit module interface width and thus thematch half-width (32-bit) memory channel retained to the S0 memorychannel. Similarly, when the logical width of the S0 channel is halvedagain from 32 bits to 16 bits (e.g., as in the four-moduleconfiguration), the memory devices of the S0 module may be reprogrammedto have a x2 data interface width as shown at 434 and thus establish a16-bit module data width to match the new channel width. Finally, whenthe logical width of the S0 channel is halved yet again from 16 bits toeight bits (e.g., as in the eight-module configuration), the memorydevices of the S0 module may again be reprogrammed to have a x1 datainterface width as shown at 436 and thus establish an 8-bit module datawidth to match the 8-bit memory channel width. Note that the modulesinserted into the expansion slots may also be programmable width modulesand thus programmed according to the width of the memory channelallocated to their respective sockets. Alternatively, any or all ofthose memory modules may have fixed widths as required by the socketsinto which they are inserted. In that regard, none of the memory modulesin the system need have programmable widths, with those having widthslarger than the available channel widths for a given module populationremoved from the system in favor of narrower-width modules.

Reflecting on FIG. 5, it should be noted that numerous details may bevaried in alternative embodiments. For example, different interfacewidths, memory devices per module, memory channel widths, and so forthmay be employed. Also, the specific I/O circuits (or pins) that aredisabled for a given width configuration may vary. For example, in thex4 memory device configuration (432), the disabled I/O circuits may bedisposed adjacent one another (e.g., top four I/O circuits or bottomfour I/O circuits disabled) instead of being interleaved with enabledI/O circuits as shown. Further, memory module 411 or any of the memorymodules discussed herein may be buffered modules (e.g., buffer ICdisposed on memory module and coupled between the on-module memorydevices and the module interconnects as in a fully-buffered DIMM(FBDIMM)) and the programmable width feature as descried above inrelation to individual memory devices could alternatively be implementedwithin the on-module buffer IC.

FIG. 6 illustrates an exemplary sequence of operations that may becarried out within an asymmetric-channel memory system to determine thesocket loading configuration and program corresponding configurationvalues within a memory interface IC and, if present, programmable-widthmemory devices. At 451, the characteristics of the module population aredetermined, for example, by attempting to read a serial-presence-detect(SPD) component (452 a) or other non-volatile memory included on thememory module to record module characteristics such as thequantity/capacity/capability of memory devices, number of ranks, etc.;attempting to write-and-read back operations to ascertain modulepresence (452 b); querying another source of configuration information(452 c), and so forth.

At 453, the possible steering configuration (there may be more than one,particularly where the modules installed in a given socket are unable tosupport the bandwidth allocable to that socket) are determined based onthe characteristics of the module population. At 455, a steeringconfiguration is selected (e.g., in response to user selection (456 a),by looking up a previously recorded selection by a user or systemdesigner (e.g., in a hardware look-up table or stored as part of asoftware program) (456 b), by applying the default steeringconfiguration corresponding to the module population characteristics(456 c), etc.). At 457, the steering logic is configured in accordancewith the selected steering configuration for example, by programming aregister within the memory interface IC (or establishing the state ofoff-chip switch elements if such configurability is supported) inaccordance with the selected steering configuration. At 459,programmable width memory devices, if present within the modulepopulation, may be programmed in accordance with the selected steeringconfiguration to establish matching logical channel widths and on-moduledata interface widths.

The foregoing operations may be effectuated, in whole or part, throughexecution of machine-executable program code. The program code (i.e.,sequences of instructions and related data) may be recorded on one ormore computer-readable media for later retrieval and execution withinone or more processors of a special purpose or general purpose computersystem or consumer electronic device or appliance. Computer-readablemedia in which such instructions and data may be embodied include, butare not limited to, machine-readable storage media in various forms.Examples of such machine-readable media include, for example and withoutlimitation, optical, magnetic or semiconductor storage media such asfloppy disk, CD, DVD, active RAM within a computer, or any other type ofphysical device from which the instructions may be extracted under fullor partial control of a machine.

The various circuits disclosed herein may be described using computeraided design tools and expressed (or represented), as data and/orinstructions embodied in various computer-readable media, in terms oftheir behavioral, register transfer, logic component, transistor, layoutgeometries, and/or other characteristics. Formats of files and otherobjects in which such circuit expressions may be implemented include,but are not limited to, formats supporting behavioral languages such asC, Verilog, and VHDL, formats supporting register level descriptionlanguages like RTL, and formats supporting geometry descriptionlanguages such as GDSII, GDSIII, GDSIV, CIF, MEBES and any othersuitable formats and languages. Computer-readable media in which suchformatted data and/or instructions may be embodied include, but are notlimited to, computer storage media in various forms (e.g., optical,magnetic or semiconductor storage media, whether independentlydistributed in that manner, or stored “in situ” in an operating system).

When received within a computer system via one or more computer-readablemedia, such data and/or instruction-based expressions of the abovedescribed circuits may be processed by a processing entity (e.g., one ormore processors) within the computer system in conjunction withexecution of one or more other computer programs including, withoutlimitation, net-list generation programs, place and route programs andthe like, to generate a representation or image of a physicalmanifestation of such circuits. Such representation or image maythereafter be used in device fabrication, for example, by enablinggeneration of one or more masks that are used to form various componentsof the circuits in a device fabrication process (i.e., implementing thecircuits in an integrated circuit die or dice).

In the foregoing description and in the accompanying drawings, specificterminology and drawing symbols have been set forth to provide athorough understanding of the present invention. In some instances, theterminology and symbols may imply specific details that are not requiredto practice the invention. For example, any of the specific numbers ofbits, signal path widths, signaling or operating frequencies, componentcircuits or devices and the like may be different from those describedabove in alternative embodiments. Additionally, the various signalinglinks and other interconnections between circuit elements or blocks maybe shown as buses or as single signal lines. Each of the buses mayalternatively be a single signal line, and each of the single signallines may alternatively be buses. Signals and signaling paths shown ordescribed as being single-ended may also be differential, andvice-versa. A signal driving circuit is said to “output” a signal to asignal receiving circuit when the signal driving circuit asserts (ordeasserts, if explicitly stated or indicated by context) the signal on asignal line coupled between the signal driving and signal receivingcircuits. The expression “timing signal” is used herein to refer to asignal that controls the timing of one or more actions within anintegrated circuit device and includes clock signals, strobe signals andthe like. The term “coupled” is used herein to express a directconnection as well as a connection through one or more interveningcircuits or structures. Integrated circuit device “programming” mayinclude, for example and without limitation, loading a control valueinto a register or other storage circuit within the device in responseto a host instruction and thus controlling an operational aspect of thedevice, establishing a device configuration or controlling anoperational aspect of the device through a one-time programmingoperation (e.g., blowing fuses within a configuration circuit duringdevice production), and/or connecting one or more selected pins or othercontact structures of the device to reference voltage lines (alsoreferred to as strapping) to establish a particular device configurationor operation aspect of the device. The terms “exemplary” and“embodiment” are used to express an example, not a preference orrequirement.

While the invention has been described with reference to specificembodiments thereof, it will be evident that various modifications andchanges may be made thereto without departing from the broader spiritand scope. For example, features or aspects of any of the embodimentsmay be applied, at least where practicable, in combination with anyother of the embodiments or in place of counterpart features or aspectsthereof. Accordingly, the specification and drawings are to be regardedin an illustrative rather than a restrictive sense.

What is claimed is:
 1. A method of operation within a memory-controlintegrated circuit (IC) having internal data conductors and distinctfirst and second data interfaces, the first data interface having twiceas many input/output (I/O) transceivers as the second data interface,the method comprising: coupling all the internal data conductorsexclusively to the I/O transceivers of the first data interface in afirst memory system configuration in which the first data interface iscoupled to a memory module having a first interface width and the seconddata interface is not connected to a memory module; and coupling a firsthalf of the internal data conductors exclusively to the I/O transceiversof the second data interface while a second half of the internal dataconductors remains exclusively coupled to half the I/O transceivers ofthe first data interface in a second memory system configuration inwhich the first and second data interfaces are coupled to respectivememory modules each having an interface width less than the firstinterface width.
 2. The method of claim 1 wherein, in the first memorysystem configuration, the I/O transceivers of the first data interfaceare coupled to the memory module having the first interface width viarespective first external signaling links, and, in the second memorysystem configuration, the I/O transceivers of the second data interfaceare coupled to one of the memory modules having the interface width lessthan the first interface width via respective second external signalinglinks, the number of first external signaling links being twice thenumber of the second external signaling links.
 3. The method of claim 1wherein, in the second memory system configuration, the I/O transceiversof the first data interface are coupled to a first one of the memorymodules having the interface width less than the first interface widthvia respective point-to-point signaling links that are dedicated to thefirst one of the memory modules, and the I/O transceivers of the seconddata interface are coupled to a second one of the memory modules havingthe interface width less than the first interface width via respectivepoint-to-point signaling links that are dedicated to the second one ofthe memory modules.
 4. The method of claim 1 wherein the internal dataconductors comprise a plurality of write data conductors and a pluralityof read data conductors and wherein coupling all the internal dataconductors exclusively to the I/O transceivers of the first datainterface comprises coupling all the write data conductors exclusivelyto the I/O transceivers of the first data interface and to coupling allthe read data conductors exclusively to the I/O transceivers of thefirst data interface.
 5. The method of claim 4 wherein coupling all thewrite data conductors and read data conductors exclusively to the I/Otransceivers of the first data interface comprises coupling the writedata conductors respectively to the I/O transceivers of the first datainterface and coupling the read data conductors respectively to the I/Otransceivers of the first data interface such that each of the I/Otransceivers of the first data interface is coupled to a respective oneof the write data conductors and a respective one of the read dataconductors.
 6. The method of claim 1 wherein the internal dataconductors comprise write data conductors and read data conductors andwherein the number of write data conductors matches the number of readdata conductors and matches the number of I/O transceivers of the firstdata interface.
 7. The method of claim 1 wherein coupling all theinternal data conductors exclusively to the I/O transceivers of thefirst data interface in the first memory system configuration comprisesdecoupling the first half of the internal data conductors from the I/Otransceivers of the second data interface in the first memory systemconfiguration.
 8. The method of claim 1 wherein coupling the first halfof the internal data conductors exclusively to the I/O transceivers ofthe second data interface in the second memory system configurationcomprises decoupling the first half of the internal data conductors froma second half of the I/O transceivers of the first data interface. 9.The method of claim 1 wherein the second half of the internal dataconductors are coupled to a first half of the I/O transceivers of thefirst data interface by fixed interconnections and wherein coupling allthe internal data conductors exclusively to the I/O transceivers of thefirst data interface comprises switchably coupling the first half of theinternal data conductors exclusively to a second half of the I/Otransceivers of the first data interface.
 10. A memory controllerintegrated circuit (IC) comprising: internal data conductors; distinctfirst and second data interfaces to be coupled, respectively, to firstand second memory modules, the first data interface having twice as manyinput/output (I/O) transceivers as the second data interface; andsteering circuitry that: couples all the internal data conductorsexclusively to the I/O transceivers of the first data interface in afirst memory system configuration in which the first data interface iscoupled to a memory module having a first interface width and the seconddata interface is not connected to a memory module, and couples a firsthalf of the internal data conductors exclusively to the I/O transceiversof the second data interface while a second half of the internal dataconductors remains exclusively coupled to half the I/O transceivers ofthe first data interface in a second memory system configuration inwhich the first and second data interfaces are coupled to respectivememory modules each having an interface width less than the firstinterface width.
 11. The memory controller IC of claim 10 wherein, inthe first memory system configuration, the I/O transceivers of the firstdata interface are to be coupled to the memory module having the firstinterface width via respective first external signaling links, and, inthe second memory system configuration, the I/O transceivers of thesecond data interface are to be coupled to one of the memory moduleshaving the interface width less than the first interface width viarespective second external signaling links, the number of first externalsignaling links being twice the number of the second external signalinglinks.
 12. The memory controller IC of claim 10 wherein, in the secondmemory system configuration, the I/O transceivers of the first datainterface are to be coupled to a first one of the memory modules havingthe interface width less than the first interface width via respectivepoint-to-point signaling links that are dedicated to the first one ofthe memory modules, and the I/O transceivers of the second datainterface are to be coupled to a second one of the memory modules havingthe interface width less than the first interface width via respectivepoint-to-point signaling links that are dedicated to the second one ofthe memory modules.
 13. The memory controller IC of claim 10 wherein theinternal data conductors comprise a plurality of write data conductorsand a plurality of read data conductors and wherein, in the first memorysystem configuration, the steering circuitry couples all the write dataconductors exclusively to the I/O transceivers of the first datainterface and couples all the read data conductors exclusively to theI/O transceivers of the first data interface.
 14. The memory controllerIC of claim 13 wherein the steering circuitry that couples all the writedata conductors and read data conductors exclusively to the I/Otransceivers of the first data interface in the first memory systemconfiguration comprises circuitry that couples the write data conductorsrespectively to the I/O transceivers of the first data interface andthat couples the read data conductors respectively to the I/Otransceivers of the first data interface such that each of the I/Otransceivers of the first data interface is coupled to a respective oneof the write data conductors and a respective one of the read dataconductors.
 15. The memory controller IC of claim 10 wherein theinternal data conductors comprise write data conductors and read dataconductors, and wherein the number of write data conductors matches thenumber of read data conductors and matches the number of I/Otransceivers of the first data interface.
 16. The memory controller ICof claim 10 wherein the steering circuitry that couples all the internaldata conductors exclusively to the I/O transceivers of the first datainterface in the first memory system configuration comprises circuitryto decouple the internal data conductors from the I/O transceivers ofthe second data interface in the first memory system configuration. 17.The memory controller IC of claim 10 wherein the steering circuitry thatcouples the first half of the internal data conductors exclusively tohalf the I/O transceivers of the first data interface and the secondhalf of the internal data conductors exclusively to the I/O transceiversof the second data interface in the second memory system configurationcomprises circuitry that couples the first half of the internal dataconductors exclusively to a first half of the I/O transceivers of thefirst data interface and switchably decouples the second half of theinternal data conductors from a second half of the I/O transceivers ofthe first data interface.
 18. The memory controller IC of claim 10further comprising circuitry to disable the I/O transceivers of thesecond data interface to conserve power in the first memory systemconfiguration and to disable an unused half of the I/O transceivers ofthe first data interface to conserve power in the second memory systemconfiguration.
 19. The memory controller IC of claim 10 wherein thesteering circuitry comprises fixed interconnections between the firsthalf of the internal data conductors and a first half of the I/Otransceivers of the first data interface and switching circuitry toswitchably couple the second half of the internal data conductorsexclusively to either the a second half of the I/O transceivers of thefirst data interface or to the I/O transceivers of the second datainterface.
 20. A memory controller integrated circuit (IC) comprising:internal data conductors; distinct first and second data interfaces tobe coupled, respectively, to first and second memory modules, the firstdata interface having twice as many input/output (I/O) transceivers asthe second data interface; and means for coupling all the internal dataconductors exclusively to the I/O transceivers of the first datainterface in a first memory system configuration in which the first datainterface is coupled to a memory module having a first interface widthand the second data interface is not connected to a memory module; andmeans for coupling a first half of the internal data conductorsexclusively to the I/O transceivers of the second data interface while asecond half of the internal data conductors remains exclusively coupledto half the I/O transceivers of the first data interface in a secondmemory system configuration in which the first and second datainterfaces are coupled to respective memory modules each having aninterface width less than the first interface width.